1. Field of the Invention
The present invention relates to a photoelectric conversion device, and to a sensor control circuit, and an image reading device using the photoelectric conversion device. In addition, the present invention also relates to an image forming apparatus using the image reading device.
2. Discussion of the Related Art
There is market demand for a photoelectric conversion device capable of performing high speed CCD driving.
FIG. 10 is a view illustrating flow of signals in a sensor board unit for use in a related-art image reading device. A case where the image reading device is a scanner will be described.
The scanner reads an image of an original document by irradiating the image with light, and then subjecting light reflected from the original document to photoelectric conversion in a charge coupled device (CCD) 1003 disposed on a sensor board unit (SBU) 1000 to obtain electric signals of the image. The SBU includes as main components the CCD 1003 subjecting light reflected from the original document to photoelectric conversion, an analog front end (AFE) 1006 subjecting the electrical signals output from the CCD to a variety of analog processings, a timing generator (TG) 1001 generating a driving signal for driving the CCD 1003 and AFE 1006, and a CCD driver 1002 driving the CCD 1003. In FIG. 10, reference numerals 1004 and 1005 denote a buffer circuit and a condenser, respectively.
Driving signals CCD_CLK and AFE_CLK needed for driving the CCD 1003 and AFE 1006, respectively, and a variety of gate signals (hereinafter referred to collectively as GATE) are generated by the TG 1001, and then input to the CCD and the AFE, respectively. The CCD driving signal generated by the TG 1001 is supplied to the CCD 1003 via the CCD driver 1002, and the CCD subjects light reflected from an original document to photoelectric conversion to output an analog electric signal. The thus-output analog electric signal is input to the condenser 1005 via the buffer circuit 1004 (constituted of an emitter follower circuit) to be subjected to AC coupling, and then input to the AFE 1006.
In the AFE 1006, the reference black level is corrected to an internal reference voltage by a clamping portion, and image signals are sampled in a sample hold portion, followed by amplification in an amplification portion and AD conversion in an A/D converter, resulting in output of digital image data (D_sig in FIG. 10).
FIG. 11 is a block diagram illustrating a related-art image reading device.
Referring to FIG. 11, CCD driving signals (ph1, ph2, ph21, rs, and cp) generated in the TG 1001 having a clock generator (CLK_gen) 1007 are input to the CCD 1003 as φ1, φ2, φ2L, RS, and CP via the CCD driver 1002. In this regard, reference character φ1/φ2 denotes transfer clocks for subjecting signal charges produced in a photodiode (PD) (not shown) in the CCD 1003 to charge transfer on an analog shift register, and φ2L denotes a last-step transfer clock.
In addition, reference character RS denotes a reset signal for resetting signal charges accumulated in a floating capacitor (FJ), which detects a signal charge transferred to an output step, to an initial state. CP denotes a clamp signal for adjusting (clamping) the basis of the signal output from the CCD 1003 so as to be any voltage. In addition to the signals mentioned above, there is a shift gate signal for use in transferring a signal charge produced in the photodiode (PD) to the analog shift register once per line, but the signal is not illustrated in FIG. 11.
The driving signals are generated in the clock generator (CLK_gen) 1007 of the TG 1001 so as to have any timing relation to each other.
Both buffer-type drivers and inverter-type drivers can be used for the driver 1002 of the CCD illustrated in FIG. 11. However, inverter-type drivers are preferable because they provide high-speed performance.
FIGS. 12A-12C are views illustrating the primary timing constraints on the CCD driving signals. Specifically, FIG. 12A illustrates a timing constraint on φ1 and φ2 (differential compression, crosspoint), FIG. 12B illustrates a timing constraint on φ1 and φ2L (differential compression, crosspoint), and FIG. 12C illustrates a timing constraint on φ2L, RS, and CP.
As illustrated in FIGS. 12A-12C, there are timing constraints on each signal or between two signals. For example, a minimum value to be secured is set to each of the HIGH-period width (t5) of RS and the width (t7) between RS↓ and CP↓. In order to drive the CCD 1003, all the constraints have to be satisfied even when the parts constituting the clock generator are varied. Similarly, a minimum value to be secured is also set to each of t1-t4, t6 and t8.
In addition, Vx1 is a standard concerning the crosspoints of φ1↓-φ2↑ and φ1↑-φ2↓, and there is a constraint such that a crosspoint is present at a voltage not lower than a predetermined voltage.
For example, when the φ2↑ timing is delayed in FIG. 12A, the crosspoint of φ1↓-φ2↑ decreases. When the delay time of φ2↑ increases, the Vx1 becomes lower than the predetermined voltage, and thereby the constraint cannot be satisfied. In this regard, in order to satisfy the constraint, the timing of φ1↓-φ2↑ and φ1↑-φ2↓ has to be adjusted to secure the crosspoint even when the timing varies. The same is true for the Vx2 concerning the crosspoints of φ1↓-φ2↑ and φ1↑-φ2↓.
By using the conventional method illustrated in FIG. 11, the timing of the signals output from the TG can be optimized, as illustrated in FIG. 13A. However, the timing of the signals at the input terminal of the CCD 1003 is widely varied depending on various factors concerning the circuit such as signal skews in the TG 1001 and CCD driver 1002, variation of resistors and capacitors, parasitic components of a transmission line (e.g., resistor/capacitor/inductor components), and capacitance of the terminal of the CCD 1003.
Specifically, the driving circuit of the CCD has to be designed so as to have a margin sufficient to satisfy all the timing restraints even when the above-mentioned factors vary, for example, in the manufacturing process thereof. However, when performing high speed driving, the timing margin cannot be secured, and therefore it becomes difficult to satisfy all the timing constraints.
In this regard, the CCD driver 1002 illustrated in FIG. 13B is of a buffer type. When an inverter type CCD driver is used therefor, the signals have polarities opposite to those of the signals illustrated in FIG. 13A.
In this case, when the CCD 1003 is driven, various timing constraints on each signal or any two signals have to be satisfied, for example, the signal timing between any two signals has to be secured in a time period not shorter than a predetermined time period.
However, as the CCD driving speed increases, it becomes difficult to satisfy the above-mentioned timing constraints. This is because there are various variation factors concerning the circuit such as signal skews in the TG 1001 and CCD driver 1002, variation of resistors and capacitors, parasitic components of a transmission line (e.g., resistor/capacitor/inductor components), and capacitance of the terminal of the CCD 1003.
Namely, the driving circuit of the CCD 1003 has to be designed so as to have a margin sufficient to satisfy all the timing restraints even when the above-mentioned factors vary worst, for example, in the manufacturing process thereof. However, since the timing margin cannot be secured in high speed driving, it becomes difficult to satisfy all the timing constraints.
In attempting to solve the problem, there is a known technique, in which a CCD driving signal generated in a timing generator is finely delayed in pieces to generate multiple delayed signals, and then a signal having a proper timing is selected from the multiple signals to optimize the timing between signals generated in the timing generator.
However, the above-mentioned technique can optimize only the timing of signals just after the signals are output from the timing generator (TG 1001), whereas the above-mentioned timing constraints should be satisfied at the input terminal of the CCD 1003. Namely, since the signals output from the timing generator (TG 1001) are affected by the variation factors present between the TG 1001 and the CCD 1003, variation of the signal timing at the input terminal of the CCD 1003 cannot be reduced.
In attempting to solve the problem, a CCD pulse generator capable of generating a CCD driving signal and a CCD output processing signal at accurate timings is proposed. The pulse generator includes a digital delay type pulse control section which finely delays a transfer signal for driving a CCD, thereby generating a plurality of delay signals, and changes selection of these delay signals, thereby generating a CCD driving signal and/or a CCD output processing signal corresponding to the predetermined rise and fall timings, an inverted/non-inverted signal generating section which generates the inverted signal and non-inverted signal of the generated signal, a selection section which selects the turned-over signal and unturned-over signal of the generated signal, a blanking section which temporarily disables the generated signal, an output section which has an output enable function and outputs the signal selected by the selection section, and an output signal condition setting section which sets pieces of condition setting information that determine the operations of the respective sections. By finely delaying a transfer signal for driving a CCD to generate multiple delay signals, and changing selection of the multiple delay signals, it becomes possible to generate CCD driving signals (such as CCD reset signals, CCD clamp signals, and preliminary signals) and CCD output processing signals (such as sampling signals) corresponding to the predetermined rise and fall timings.
However, the above-mentioned CCD pulse generator cannot solve the problem of optimizing the signal timings at the CCD terminal, and it is difficult for the CCD pulse generator to drive a CCD at a high speed.
For these reasons, the present inventors recognized that there is a need for a photoelectric conversion device capable of performing high speed CCD driving.